中文履歷

基本資料

中文姓名: 鍾懿軒
英文姓名: I-Shuan Tsung
出生日期:


聯絡資料

Email: istsung@gmail.com
聯絡電話:
聯絡方式:
通訊地址:
個人網頁: http://istsungcn.blogspot.com/


學歷

Master of Electrical and Computer Engineering
The University of Texas at Austin, USA 08/2005 - 12/2008

學士 資訊工程系
國立交通大學, 新竹, 台灣 09/2000 - 06/2004


工作經歷

Apple Inc., Mobile Silicon Group, Verification Engineer 10/2009 -

約聘工程師 財團法人資訊工業策進會 網路多媒體研究所 3D繪圖組 03/2009 -
Graphic processing unit shader core ISA specification design, RTL design, simulation, systhesis.
Design shader core hardware for OpenGLES 2.0 SL.

Co-op Engineer Advanced Micro Devices 01/2007 - 01/2008
Graphic processing unit floating-point arithmetic unit microcode documentation and analysis.
Develop automatic board testing user interactive program using C# and Visual Studio 2005.
GUI implementation using C# and Visual Studio 2005.


學習經歷

• Floating-point addition unit simulation using Verilog, Floating-point Arithmetic and Design
  Responsible for designing pipeline FP adder architecture and work assignments for the team.
  Direct experience in designing and simulating short pass FP adder in Verilog.
  Direct experience in project integration, verification and testing on Synopsys VCS.
• IA-32 microprocessor design and implementation in Verilog, Microarchitecture
  Participate in team effort to design and implement an Intel IA-32 microprocessor at gate level.
  Responsible for designing and implementing the backend pipeline including memory access, execution, write back stages.
  Direct experience in project integration, verification and testing on Synopsys VCS.
• Microprocessor design and simulation in C, Computer Architecture
  Design and simulate a microprocessor native in LC-3b ISA using C including virtual memory, exception and interrupt, unaligned access, and pipelining.
• Integer multiplier simulation using Verilog, Computer Arithmetic and Design
• Simulate and compare Wallace multiplier in Verilog. Verify and debug with Synopsys VCS.
• DRM receiver hardware simulation using SystemC, System-on-chip Design
  Design the receiver architecture and divide it into parts for team work.
  Integrate all parts and verify on SystemC platform.
• An Evaluation of Optimization Algorithm for Mini-JIT Compiler, Senior Project
  Evaluate folding algorithm performance on an x86 native environment.
  Analyze and simulate Folding optimization algorithm embedded in Mini-JIT in C.
• Design and simulate MIPS microprocessor in Verilog, Computer Organization

社團經驗

Toastmasters International 中華民國國際演講會 04/2009 -
國立交通大學攝影社長 09/2001 - 06/2002
中華民國第26屆竹湖攝影營執行策劃 07/2002
攝影社社團聯展，參與策劃與展出 04/2002
交大清華梅竹賽攝影組組長 07/2001 - 03/2002
國立交通大學校運混攝影比賽執行策劃 11/2001


語文能力

中文 聽說讀寫 精通
英文 聽說讀寫 精通
日文 聽說讀寫 略懂


技能專長

程式語言: Verilog, perl, C, C++, Java, x86 assembly, HTML
CAD Tool: NCVerilog, Synopsis VCS, Verdi, Design Compiler
OS: Linux, Unix, Windows, OS X

Other Tool: MS Office


認證資格

TOEFL 267
GRE 1200
GMAT 690